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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:13:54 03/14/2012 
-- Design Name: 
-- Module Name:    koppeling_ram_idram - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity koppeling_ram_idram is
end koppeling_ram_idram;

architecture Behavioral of koppeling_ram_idram is

begin	Inst_Read_UART_RAM: Read_UART_RAM PORT MAP(
		Data_in => ,
		Reset => ,
		Klok => ,
		Buffer_full => ,
		Data_present => ,
		read_buffer => ,
		Write_RAM => ,
		Done => ,
		Adres_RAM => ,
		Data_RAM => 
	);
	
end Behavioral;

